As we move deeper into the digital age, some of us may wonder how much faster our cameras can process images while others may rue the carbon footprint left by constantly recharging our cell phone and iPod batteries. The good news, it seems, is that high speed processing and green technology can go hand in hand to power everyday electronics.
The strategy for digital devices lies in the design of simple yet powerful microchips, each containing many processors that can self-adjust energy usage, according to a team of UC Davis engineers.
Professor Bevan Baas and his students in the department of electrical and computer engineering have successfully created and tested a revolutionary 167-processor chip that combines the coveted features of high speed and energy efficiency.
The fully reprogrammable and highly configurable chip called AsAP measures 5mm per side and clocks in at a maximum 1.2 GHz.
“We think it’s the highest clock frequency processor that’s been designed [and built] in a university,” Baas said.
Although not designed with a computer CPU in mind, digital signal processing (DSP) chips like AsAP are commonly found in devices with specialized applications including cell phones, MP3 players, video equipment, anti-lock brakes and some medical imaging machines.
Not only can AsAP run targeted applications up to 10 times faster than what is currently available, its efficiency allows batteries to last up to 75 times longer than they would if they were powering common commercial DSP chips, Baas said.
While multi-core chips typically spread task workloads over multiple processors, a breakthrough feature of the AsAP design is that each processor on the chip can change both its speed and power supply according to activity level. Like a computer that goes into sleep mode, a processor in AsAP conserves energy by switching to the minimum speed required to perform a particular task, or by simply powering down when idle.
“The energy saving technology that we have developed should have an impact on prolonging the battery life of portable devices,” said Wayne Cheng, a former graduate student who designed the power saving circuit strategy for the AsAP. “In addition, as processor architectures move toward more multi-core implementations, our research would pave the way to much greener computers.”
Baas and his team used standard technology and design tools to build the new AsAP chip based on their earlier version, which has 36 identical processors and runs at a maximum 610 MHz. Even when it was announced in 2006, the first AsAP was considered the fastest processor designed in a university.
Integrated improvements include larger memory and three special processors that facilitate tasks for specific applications like high-definition video, WiFi communication, security and encryption, said graduate student Dean Truong, a key designer of the second generation AsAP.
From design to final product, Baas‘ students had many hurdles to jump, not least of which was to exhaustively test every feature and function that the new chip is designed for.
“Another major challenge that I was responsible for was to make sure every part in the chip received enough power,” said graduate student Tinoosh Mohsenin. “This is much like the job PG&E has to do when they layout power grids for cities, but on a very small scale. This is important because if some parts don’t get enough power, they may not operate correctly or as fast as they should.“
Baas and his students plan to continue developing applications for AsAP including software designed radios (Bluetooth and GPS cell phone features are some examples), image processing, scientific modeling, hearing aids and portable ultrasounds for medical imaging. At the same time, they are thinking up innovations for the third generation, which include plans for a 4,000-processor chip.
Baas has no plans to market the new chip but believes that the ideas behind AsAP could eventually find their way into commercial DSP technology.
“The whole trend toward multi-processors is definitely a strong one,” he said.
Details of the new AsAP design were published in the April issue of IEEE Journal of Solid-State Circuits.
ELAINE HSIA can be reached at features@theaggie.org.
